MEMORY ARCHITECTURE

• 1MB memory (20 address lines)

• Interrupt Vector table (1Kbyte)

• RAM (connected to lower memory)

• EPROM (connected to upper memory)

EPROM

• Pinout

• Address bus (depend on size)

• Data bus (8 bit)

• Read enable pin (OE) (Active low pin)

• Programming voltage pin (VPP)

• Chip Enable pin (CS) (Active low pin)

• EPROM Size decoding (i.e. 2716 is 2K EPROM)

RAM

• Pinouts

• Address bus (depend on size)

• Data bus (8 bit)

• Read enable pin (OE) (Active low pin)

• Write enable pin (WR) (Active low pin)

• Programming voltage pin (VPP)

• Chip Enable pin (CS) (Active low pin)

• RAM Size decoding (i.e. 2716 is 2K EPROM)

 NAND GATE DECODING

• Interface 2K EPROM with microprocessor using Nand gate decoding

• For Figure see lectures (webpage\figures\lect-4-5-6\nand-gate.doc).

 OR GATE DECODING

• Interface 1K RAM with microprocessor using OR gate decoding

• For Figure see lecture (webpage\figures\lect-4-5-6\or-gate.doc).

EPROM bank interface

• Interface eight 1K EPROM's with microprocessor

• Only one EPROM can be selected at a time.

• Same procedure can be used for interfacing RAMS.

• For Figure see lecture