8088 PINOUTS

Microprocessor 8088 is a 40-pin integrated circuit

Theses pin can be divided into groups

1. 20 pins carry address & data lines
2. 4 pins ( IO/MEM, ALE, DEN, DT/R) are used for data & address bus demultiplexing
3. RD & WR pins are made active low by microprocessor whenever microprocessor is sending or receiving data.
4. INTR, INTA, NMI are interrupt pins
5. READY pin is used for wait state insertion
6. Clock pin is connected between 8284 & 8088
7. Two pins are ground with one VCC
8. MIN/MAX pin is made high whenever two microprocessors are used & this pin is a low when one microprocessor is used
9. RESET pin is used to reset the microprocessor
10. HOLD & HOLDA pins are used when DMA is required

DEMULTIPLEXING OF 8088

8088 demultiplexed using 74LS245 (Bi-directional octal buffer) & 74LS373 (20 pin octal latch)

For Figure See Lecture (webpage\figures\lect-1-2-3\8088demux.doc).

8284 CLOCK GENERATOR

8284 Clock generator is an 18 pin peripheral integrated circuit. The pin explanation is as follows.

• (AEN1 &AEN) are address enable pins. These pins with (RDY1 & RDY2) are used for wait state insertion.
• READY pin is connected to 8088 microprocessor to provide Wait State to the processor.
• CLK pin is used to provide clock to the microprocessor.
• Single GROUND & VCC pin is also available.
• CSYNC pin is used only whenever crystal is not used. If the internal crystal oscillator is used then this pin must be grounded.
• RESET pin is used to provide reset signals to 8088.
• Reset circuit is connected to RES pin.
• OSC pin provides same frequency as the crystal.
• PCLK pin provides clock to other peripherals. This clock is one sixth of the main clock.
• EFI is the external frequency input pin. This pin is used only if there is logic one at the pin F/C.
• F/C is used to identify 8284 whether crystal is connected or frequency is provided by some other source.
• Crystal is connected at pins X1 & X2.
• ASYNC pin is used for wait state circuitry.

BUS CYCLE

The bus cycle consists of four timing states. The description is as follows.

• The first state is the T1 State. This state is called as Address State. During this state ALE signal is enabled while DEN is disabled. DT/R signal has no significance during this state.
• The second state is the T2 State. This is READ or WRITE State. During this time DEN is enabled while ALE is disabled. DT/R pin during this state defines that whether 8088 need to receive or transmit data. In case of READ operation RD pin is held low while WR is high. If write operation then WR is held low & RD is disabled & the data that is required to be sent is also needed.
• Data bus is sampled at the end of T3 State. In case of wait state READY pin is checked at the center.
• All the signals are initialized at the end of T4 State.

For Figure see lecture.

WAIT STATES

• RDY1 & RDY2 controls ready i.e. they make ready either 1 or 0.
• Ready pin is checked at the end of T2 & again at the middle of T3.
• For one wait state system Ready pin is zero at the end of T2 & becomes 1 at the middle of Tw.
• We use SIPO shift register for wait state generation.
• For 1^st clock cycle QA becomes 1 & for 2^nd clock edge QB becomes 1 & hence all becomes 1 after the specified clock pulses.
• RD & WR are low during T2 to T4 (any one of them) & they are high during T1.
• During T2 any one of RD or WR becomes low.
• Also INTA is high during T1.
• After low pulse at CLR QA will becomes 1 on first positive clock edge.
• Connect QB to RDY1 we will get two wait states.
• Similar if QC is connected to RDY1 Then three wait states are added & so on.
• Wait State will only be added when slow chip is being used.
• For fast chip no wait states will be generated or required.
• One circuit (74LS164 circuit) will add only fixed wait states.

For figure see lecture (webpage\figures\lect-1-2-3\wait.doc).